rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9005b one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 12-bit, 10 msps a/d converter functional block diagram flash a/d + dac fine encode sum amp l o g i c a r r a y 5 4 timing circuits t/h 45 24 ad9005b 9 20 analog input encode t/h out a/d in digital data outputs features complete 12-bit a/d converter includes track-and-hold, reference and timing bipolar analog input ( 6 1.024 v) up to 10 msps sampling rate low power dissipation: 3.2 w low harmonic distortion mll-std-883-compliant versions available applications radar digital receivers electro-optics medical scanners signal intelligence spectrum analyzers general description the ad90 05b is a complete 12-bit a/d converter that includes on-board track-and-hold amplifier, voltage reference, and tim- ing circuits. featuring sampling rates from dc to 10 msps, the ad9005b uses a subranging converter architecture to achieve high speed and high resolution. dynamic performance includes an snr of 64 db and harmonic distortion of C72 dbc with a 4.3 mhz analog input. this unit replaces its predecessor, the ad9005a. the ad9005b uses a higher level of integration than the earlier design to pro- vide increased performance, better reliability and reduced cost. the ad9005b requires only +5 v and C5.2 v supplies (elimi- nating the +15 v and C15 v requirements of the ad9005a). the ad9005b will operate without board modification in ad9005a sockets because +15 v and C15 v pins are not internally connected. all grades are fully tested for dynamic performance. critical to the performance of the ad9005b is the use of ad- vanced bipolar integrated circuits, custom designed for this device and manufactured by analog devices. the ad9005b is ttl-compatible with offset binary outputs. it is available in a 46-lead hermetic metal dip in two temperature ranges: 0 c to +70 c commercial range and C55 c to +125 c military range (case temperature). page 1 of 8 obsolete
C2C rev. 0 ad9005bCspecifications electrical characteristics commercial military 0 8 c to +70 8 c C55 8 c to +125 8 c test ad9005bkm ad90005btm/kj parameter temp level min typ max min typ max units resolution +25 c i 12 12 bits lsb weight full v 0.5 0.5 mv static accuracy differential nonlinearity +25 c i C1.0 0.5 +1.0 C1.0 0.5 +1.0 lsb full vi C1.0 +1.5 C1.0 +1.5 lsb integral nonlinearity +25 ci 1.0 1.25 1.0 1.25 lsb full iv 2.25 2.25 lsb no missing codes full vi guaranteed guaranteed gain error +25 ci 0.5 1.0 0.5 1.0 % fs full vi 2.0 2.0 % fs offset error +25 ci 4 15 4 15 mv full vi 30 40 mv analog input input voltage range full v 1.024 1.024 v p-p input resistance full vi 900 1000 1100 900 1000 1100 w input capacitance +25 cv 8 8 pf large signal input bandwidth 3 full v 38 38 mhz dynamic characteristics 5 maximum conversion rate full i 10 10 msps output data delay 6, 9 (t pd ) +25 c v 90 90 ns aperture delay (t a ) +25 cv 9 9 ns aperture uncertainty +25 c iv 10 20 10 20 ps rms transient response (to 1 lsb) 7 +25 c iv 120 120 ns overvoltage recovery time 8 +25 c iv 250 250 ns (to 1 lsb) harmonic distortion 10, 4 f in = 540 khz + 25 c iv C73 C78 C73 C78 dbc f in = 2.3 mhz +25 c i C68 C72 C68 C72 dbc full vi C67 C66 dbc f in = 4.3 mhz +25 c i C66 C72 C66 C72 dbc full vi C65 C63 dbc signal to noise ratio 11, 4 f in = 540 khz +25 civ 6567 6567 f in = 2.3 mhz +25 c i 63 65 63 65 db full vi 63 60 db f in = 4.3 mhz +25 c i 62 64 62 64 db full vi 61 60 db two-tone intermodulation distortion 12 f in = 2.2 mhz + 2.3 mhz +25 c v C75 C75 dbc encode input 14 logic l voltage full iv 2.0 2.0 v logic 0 voltage full iv 0.8 0.8 v logic 1 current full i 150 150 m a logic 0 current full i 150 150 m a input capacitance +25 cv 5 5 pf encode pulse width (high) +25 civ2525ns (+v s = +5 v, Cv s = C5.2 v, unless otherwise noted) absolute maximum ratings 1 positive supply voltage (+v s ) . . . . . . . . . . . . . . . . . . . . . +6 v negative supply voltage (Cv s ) . . . . . . . . . . . . . . . . . . . . C6 v analog input voltage (pin 45) . . . . . . . . . . . . . . . . . 3.0 v dc digital input voltage . . . . . . . . . . . . . . . . . . . . . C0.5 v to +v s digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 4 ma operating temperature range (case) ad9005bkm . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c ad9005btm . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature 2 . . . . . . . . . . . . . . . . . . . . . . . . +175 c lead soldering temperature (10 sec) . . . . . . . . . . . . . +300 c page 2 of 8 obsolete
C3C rev. 0 ad9005b commercial military 0 8 c to +70 8 c C55 8 c to +125 8 c test ad9005bkm ad9005btm parameter temp level min typ max min typ max units digital outputs logic l voltage (2 ma source) full i 2.4 2.4 v logic 0 voltage (4 ma sink) full i 0.4 0.4 v logic coding full iv offset binary offset binary power supply supply voltage +v s full vi 4.75 5.0 5.25 4.75 5.0 5.25 v supply current analog +v s full vi 180 240 180 240 ma supply current digital +v s full vi 43 80 43 80 ma supply voltage Cv s full vi C4.95 C5.2 C5.45 C4.95 C5.2 C5.45 v supply current analog Cv s full vi 210 320 210 320 ma supply current digital Cv s full vi 65 110 65 110 ma nominal power dissipation full vi 3.2 4.0 3.2 4.0 w psrr 13, 15 +25 c i 0.01 0.02 0.01 0.02 %/% notes 1 1 absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit ma y be impaired. functional oper- ation under any of these conditions is not necessarily implied. exposure to absolute rating conditions for extended periods of time may affect device reliability. 1 2 maximum junction temperature should not be allowed to exceed +175 c. hybrid thermal model: t junction = t ambient + p dissipation ( q ca ) + t s C t c ) max where (t s C t c ) max = 10 c 46-lead metal dip: q ca = 14 c/w in still air; q ca = 6 c/w with 500 lfpm air flow. 1 3 determined by 3 db reduction in reconstructed output. 1 4 1nput at 1 db below full scale. 1 5 measured at 10 mhz encode rate. 1 6 measured from encode in to data out for lsb only. 1 7 for full-scale step input; 12-bit accuracy is attained in the specified time. 1 8 recovers to 12-bit accuracy in specified time following 200% full-scale input voltage. 1 9 excludes pipeline delay of two clock cycles (see timing diagram). 10 worst case spurious in-band signal relative to input level. 11 rms signal to rms noise, including harmonics. 12 worst case spurious in-band signal relative to level of input tones, which are both C7 db below full scale. 13 sensitivity of full-scale gain error with respect to power supply variation within supply min/max limits. 14 encode signal rise and fall times should be less than 5 ns for normal operation. transition from 0 to 1 initiates conversio n. 15 psrr is tested over given voltage range. specifications subject to change without notice. explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. iii C periodically sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c. 100% production tested at temperature extremes for military temperature devices. guaranteed, not tested, for com- mercial temperature range ordering guide model temperature range package description package option* ad9005bkm 0 c to +70 c 46-lead dip, commercial temperature m-46 ad9005btm C55 c to + 125 c 46-lead dip, military temperature m-46 ad9005/pcb 0 c to +70 c ad9005 evaluation board *m = hermetic metal can dip. page 3 of 8 obsolete
ad9005b C4C rev. 0 pin function descriptions pin name description 1 ground circuit ground. all grounds should be connected together near the ad9005b. 2 nc not internally connected. 3 analog +v s positive analog supply pin. nominally +5 v dc. 4 t/h out output of internal track-and-hold amplifier. connect to pin 5 for normal operation. 5 a/d in input to internal a/d encoder. connect to pin 4 for normal operation. 6 analog Cv s negative analog supply pin. nominally C5.2 v dc. 7, 8 dnc do not connect. internal test point. 9d 11 (msb) most significant bit of digital output data. 10C19 d 10 Cd 1 digital data outputs. 20 d 0 (lsb) least significant bit of digital output data. 21 digital +v s positive digital supply pin. nominally +5 v dc. 22, 23 ground circuit ground. all grounds should be connected together near the ad9005b. 24 encode convert command. ttl compatible, rising edge triggered. 25, 26 ground circuit ground. all grounds should be connected together near the ad9005b. 27C29 dnc do not connect. internal test point. 30 analog +v s positive analog supply pin. nominally +5 v dc. 31 digital Cv s negative digital supply pin. nominally C5.2 v dc. 32 ground circuit ground. all grounds should be connected together near the ad9005b. 33 nc not internally connected. 34, 35 ground circuit ground. all grounds should be connected together near the ad9005b. 36 dnc do not connect. internal test point. 37, 38 ground circuit ground. all grounds should be connected together near the ad9005b. 39, 40 dnc do not connect. internal test point. 41 nc not internally connected. 42 analog Cv s negative analog supply pin. nominally 5.2 v dc. 43 nc not internally connected. 44 nc not internally connected. 45 analog input analog input. full scale of + 1.024 v. 46 ground circuit ground. all grounds should be connected together near the ad9005b. pin designations ground nc gnd analog input a/d in analog ? s dnc analog ? s nc dnc analog +v s t/h out nc nc dnc dnc (msb) d 11 gnd d 10 gnd d 9 d 8 gnd d 6 nc d 5 d 4 d 3 gnd digital ? s analog +v s d 2 dnc d 1 dnc (lsb) d 0 dnc digital +v s gnd gnd gnd gnd encode d 7 gnd 36 46 45 42 41 40 44 43 39 38 37 35 34 33 26 32 31 30 29 28 27 25 24 dnc top view (not to scale) ad9005b 13 1 2 5 6 7 3 4 8 9 10 11 12 14 23 15 16 17 18 19 20 21 22 nc = no connect dnc = do not connect output coding analog input d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 3 +1.024 v 111111111111 1.024 v 000000000000 page 4 of 8 obsolete
ad9005b C5C rev. 0 t pd aperture delay ( t a ) n n + 1 n + 2 n + 3 n + 4 analog input encode output data n C 3 n C 2 n C 1 n n + 1 figure 1. timing diagram 1k w +5v ?.2v ad9005b ad9005b analog input encode ad9005b d x figure 2. equivalent input/output circuits +5v 1k w load resistors all capacitors in m f 10% resistors in w 5% gnd (lsb) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 (msb) d 11 ad9005b s 1 s 2 see waveforms 0.1 0.1 +5v C5.2v encode analog in t/h out a/d in digital +v s analog +v s analog Cv s digital Cv s +5v 0v f = 5mhz s 1 s 2 +1v C1v f = 250khz figure 3. burn-in circuit page 5 of 8 obsolete
ad9005b C6C rev. 0 applications information the ad9005b is a complete analog-to-digital converter. the ad9005b uses a subranging a/d architecture enhanced by hybrid technology. this includes an on-board track-and-hold amplifier, on-board references, timing circuitry and output latches. the analog input of the ad9005b is fed directly into the inter- nal track-and-hold amplifier, thus eliminating the need for ex- ternal signal conditioning in many applications. this amplifier provides low input capacitance and a bipolar ( 1.024 v) input range. normally reverse-biased schottky diodes on the input provide overrange protection. if the amplitude, bandwidth or dc voltage level of the analog input signal calls for external signal conditioning, it is advisable to use an amplifier with low har- monic distortion and low noise characteristics. selecting the amplifier may be difficult because the performance of the ad9005b will probably exceed the performance of most com- mercially available amplifiers. a notable exception is the ad9617, a wideband low noise current feedback amplifier. it is important to remember that band limiting the analog input signal can avoid aliasing during the a/d conversion process. timing in the ad9005b is critical, and careful measures must be taken to support 12-bit accuracy. one simple way to enhance the performance of the ad9005b is to synchronize the system clock to a crystal oscillator. this will minimize any clock jitter, a must for maintaining the spectral purity of analog signals near nyquist limits. because the conversion cycle begins with the rising edge of the encode signal, a fast, clean, rising edge will also help to reduce any clock jitter. when the encode signal of the ad9005b goes high, the internal track-and-hold enters the hold state; after 65 ns, it returns to track mode. in applications in which the ad9005b is slowly or intermittently clocked (i.e., in burst mode), the encode signal should be returned to a logic low state during the idle periods. the encode signal pulse width should also be adjusted so it is in the high (hold) state for a minimum of 25 ns. this en- sures that the t/h enters the hold mode before the a/d conver- sion takes place. the ad9005b has many appealing characteristics for 12-bit a/d converter applications. its dynamic performance is state-of- the art in hybrid technology. typical applications include radar, missile guidance, digital oscilloscopes, waveform analyzers, medical instrumentation, electro-optics, communications and esm. (lsb) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 (msb) d 11 ad9005b analog in 45 encode 24 ttl x-tal oscillator t/h out a/d in 4 5 digital +v s 10 m f +5v 0.1 m f 21 digital Cv s 10 m f C5.2v 0.1 m f 31 10 m f +5v analog +v s 0.1 m f 3 30 analog Cv s 10 m f C5.2v 0.1 m f 6 42 gnd 1 222325 26 32 34 35 37 38 46 20 19 18 17 16 15 14 13 12 11 10 9 digital output data analog signal figure 4. typical application page 6 of 8 obsolete
ad9005b C7C rev. 0 layout information the accuracy of a 12-bit converter, especially one with the dy- namic performance level of the ad9005b, requires that design- ers pay careful attention to printed circuit board layouts. analog signal paths should be impedance matched, with termination/ load resistors at or near package connections. analog signal paths should also be isolated from digital signal paths. other- wise digital signals can be capacitively coupled into the analog section of the circuit, degrading the overall performance of the a/d converter. digital switching noise on power supplies can also degrade converter performance. because of this noise (inherent with ttl logic), the digital power supplies of the ad9005b should be separated from the analog power supplies. in addition, each power supply should be capacitively decoupled to ground. to accomplish this, a single large value capacitor with a high reso- nant frequency (a 10 m f tantalum capacitor for example) should be used on each of the ad9005bs power supplies, at or near the package. in addition, a lower value capacitor with good high frequency characteristics (a 0.1 m f ceramic chip capacitor is recommended) should be connected to each power supply pin connection. for applications in which only single +5 v and/or C5.2 v sup- plies are available, a ferrite bead, placed in series between the analog and digital power pins, can be used to isolate the digital noise from the analog circuits. noise on the circuit ground is often the limiting factor in a/d converter performance. perhaps the most critical concerns of circuit layout are the ground connections. to reduce ground noise, a two-sided printed circuit board is recommended, the component side being reserved (as much as possible) for a single, low impedance ground plane. the other side should be used for all (possible) power and signal connections. each of the ground connections of the ad9005b should be connected to the ground plane, and most of the area under the ad9005b should be part of this ground plane. the metal case of the ad9005b is connected to ground. operation of the ad9005b requires that pin 4, the output of the internal track-and-hold, be connected to pin 5, the input to the ad9005bs a/d converter circuitry. a suggested layout, illustrating this connection, is shown below. a final suggestion regarding circuit layout concerns the use of sockets. ideally, parts should be soldered into boards in final designs. if sockets must be used, individual pin sockets are recommended to avoid lead inductance and capacitive coupling between adjacent pins. pin sockets are available from amp, part #6-330808-0. suggested layout figure 5. gnd plane side (as viewed from top) figure 6. solder side (as viewed from top) figure 7. component mounting (as viewed from top) page 7 of 8 obsolete
ad9005b C8C rev. 0 c1874aC1C5/97 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 46-lead metal dual in-line can 0.100 (2.54) 0.005 (0.127) 22 places noncumulative 1.300 (33.020) 0.010 (0.254) 1.590 (40.386) max 0.140 (3.556) 0.010 (0.254) 0.090 (2.286) 0.010 (0.254) 2.200 (55.880) 0.006 (0.1524) 2.390 (60.706) max 0.210 (5.33) min 0.060 0.005 (1.52 0.127) 0.245 max id bead and esd triangle (on top) denote pin 1 80 77 65 0.1 1 10 74 71 68 ?0 ?7 ?5 ?4 ?1 ?8 snr ?db harmonics ?dbc analog input frequency ?mhz (encode rate = 10msps) 3rd harmonic 2nd harmonic snr w/o harmonics snr with harmonics figure 9. dynamic performance (@ +25 c) 400 w 400 w 50 w ad9617 50 w analog in ttl x-tal oscillator 74hc04 (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 (msb) d11 encode analog in t/h out a/d in ad9005b clock 74hc374 latch bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 i out dac ad9713b connector reconstructed waveform 50 w figure 8. evaluation circuit page 8 of 8 obsolete
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